The present invention relates to a semiconductor device and a manufacturing technology therefor, and particularly to a technology effective for application to a nonvolatile memory semiconductor device having electrically erasable programmable parallel connection-type nonvolatile memory cells.
In a nonvolatile memory semiconductor device, nonvolatile memories capable of electrically writing data therein and erasing the same therefrom are able to rewrite or update data in a state of being built onto a wiring board, for example and are easy to use. Therefore, they have widely been used in various products that need the memories.
In particular, an electrical batch erasure-type EEPROM (Electric Erasable Programmable Read Only Memory: hereinafter called a xe2x80x9cFlash memoryxe2x80x9d) has the function of collectively electrically erasing data lying in a predetermined range (including all the memory cells or a predetermined memory cell group in a memory array) of the memory array. Further, since the flash memory has a one-transistor stacked gate structure, the downscaling of each cell is put forward and expectations on high integration thereof are also high.
In the one-transistor stacked gate structure, one nonvolatile memory cell (hereinafter abbreviated simply as xe2x80x9cmemory cellxe2x80x9d) basically comprises one two-layer gate MISFET (Metal Insulator Semiconductor Field Effect Transistor). The two-layer gate MISFET is formed by providing a floating gate electrode on a semiconductor substrate with a tunnel oxide film interposed therebetween and stacking a control gate electrode thereon with an interlayer film interposed therebetween.
The storage of data in the flash memory is carried out by injecting electrons into the floating gate electrode or pulling out or extracting the electrons from the floating gate electrode. For example, a NOR type flash memory typified by a parallel connection-type nonvolatile memory carries out data processing in the following manner.
In order to perform the writing of data, a source region and a substrate are grounded and a relatively high voltage is applied to a control gate electrode and a drain region. Thus, electrons move or travel on a channel region near the surface of the substrate from the source region to the drain region at high speed, and electrons each having obtained sufficiently high energy in the neighborhood of the drain region in which the channel region is pinched-off, result in hot electrons. The hot electrons are capable of jumping over a potential barrier of a gate insulating film placed under a floating gate electrode. Owing to an electric field produced by the control gate electrode, the hot electrons get over the barrier of energy and are attracted to and injected into the floating gate electrode. This injection is normally called xe2x80x9chot electron injectionxe2x80x9d or xe2x80x9cchannel injectionxe2x80x9d. In the present specification, it will hereinafter be called xe2x80x9cHE injectionxe2x80x9d. By doing so, the floating gate electrode is negatively charged and the threshold value as viewed from the control gate electrode becomes higher than a predetermined value. This state in which the threshold voltage is higher than the predetermined value, is called a xe2x80x9cdata-written statexe2x80x9d, e.g., a logic xe2x80x9c0xe2x80x9d.
Further, FN tunneling (Fowler-Nordheim tunneling) of the thin gate insulating film placed below the floating gate electrode carries out the erasing of data. When, for example, a relatively high voltage is applied to the control gate electrode in a state in which the source and drain regions are open, electrons lying in the floating gate electrode are pulled out to the semiconductor substrate placed under the floating gate electrode (tunnel emission), and the potential at the floating gate electrode is returned to neutrality, so that the threshold voltage as viewed from the control gate electrode becomes lower than a predetermined value. This state in which the threshold voltage is lower than the predetermined value, is called a xe2x80x9cdata-erased statexe2x80x9d, e.g., a logic xe2x80x9c1xe2x80x9d. The FN tunneling can be effected even on a semiconductor region for the source region or drain region located under the floating gate electrode except for the substrate.
Furthermore, in order to carry out the reading of data, a voltage, which ranges from about 3 V to about 5 V, for example, is applied to the control gate electrode. Since, at this time, no current flows in a channel region in the case of a memory cell with data written therein but a current flows in a channel region in the case of a memory cell with data erased therefrom, the logics xe2x80x9c1xe2x80x9d and xe2x80x9cSxe2x80x9d can be distinguished from each other, and hence information can be read from the memory cell.
In an actual memory cell array, a plurality of word lines extending in a row direction and a plurality of bit lines extending in a column direction are placed so as to intersect one another. Memory cells are respectively disposed at points where the word lines and the bit lines intersect. The drain regions of the respective memory cells are connected to their corresponding bit lines, and the source regions of the respective memory cells are connected to their corresponding source lines. Thus, when data is written into the corresponding memory cell, both a word line (hereinafter called a xe2x80x9cselected word linexe2x80x9d) and a bit line intended for writing are respectively set to a relatively high voltage. When data is erased from the corresponding memory cell, a selected word line may be set to a relatively high voltage in a state in which a bit line and a source line are open. Such a parallel connection-type nonvolatile memory semiconductor device has been described in U.S. Pat. No. 4,868,619.
Incidentally, while the high integration of the flash memory is put forward on the strength of the progress of extensive technologies such as a micro-fabrication technology, a new circuit technology or a downsized package technology, etc., various problems incident to the scale-down or downsizing of each memory cell arise. Even as to this, however, the scale-down of each memory cell is realized while achieving an improvement in memory cell structure, a change in operating voltage, etc.
For example, in the flash memory having the cell layout of NOR type, which corresponds to one parallel connection type discussed by the present inventors, a problem has been clarified in that upon a punch-through phenomenon due to a short channel effect in the main, and writing, an increase in leak current developed in each memory cell (hereinafter called xe2x80x9cnon-selected memory cellxe2x80x9d) unintended for writing, which is connected to each memory cell (hereinafter called xe2x80x9cselected memory cellxe2x80x9d) intended for writing with a bit line shared therebetween will reduce the reliability of the flash memory.
As for the short channel effect, however, an n type semiconductor region, which constitutes a drain region, is surrounded by a punch-through stopper layer indicative of p type conductivity to allow the prevention of punch-through. Namely, the major cause of the short channel effect resides in that a depletion layer developed from the drain region of each memory cell reaches the source region and a current flows between the source and drain regions. However, the suppression of the extension of the depletion layer produced from the drain region by the punch-through stopper layer allows the avoidance of the generation of the short channel effect even if a gate length is about 0.3 xcexcm.
A method of applying a negative voltage to a word line (hereinafter called xe2x80x9cnon-selected word linexe2x80x9d) unintended for writing has been adopted to cope with the increase in the leak current developed in the non-selected memory cell. It is thus possible to control or suppress the leak current developed in each non-selected memory cell having a drain region to which a voltage is applied upon writing. Incidentally, for example, Unexamined Patent Publication No. Hei 5(1993)-182473 has been disclosed as an example of the Patent which has described a flash memory wherein a leak blocking voltage is applied to a non-selected word line upon writing.
On the other hand, when the scale-down of each memory cell is put forward and the width (hereinafter called xe2x80x9cgate lengthxe2x80x9d) extending in the source and drain regions, of the gate electrode becomes smaller than 0.3 xcexcm, it is considered that there is need to simultaneously apply a method of forming a punch-through stopper layer to control or suppress a short channel effect, and a method of applying a negative voltage to each non-selected word line to suppress a leak current developed in each non-selected memory cell.
As a result of discussions by the present inventors, however, it has been cleared that when the two method are simultaneously applied, a so-called drain disturb phenomenon occurs wherein the threshold voltage of each non-selected memory cell varies upon writing.
Namely, in a non-selected memory cell having a drain region to which a positive voltage (e.g., 6 V) is applied, a depletion layer of an n type semiconductor region, which constitutes the drain region, is hard to extend due to a punch-through stopper layer and an electric field is made steep. In addition to it, the curvature or bending of a band is rendered steep due to a negative voltage (e.g., xe2x88x922.5 V) applied to a non-selected word line on the surface of a channel region near the drain region, and each electron-hole pair is dissociated at a drain end to thereby make it easy to cause avalanche hot carriers. Thus, the hot holes are injected to a floating gate electrode, so that the threshold voltage is varied.
With a view toward suppressing the variation in threshold voltage, there is need to relax the electric field at the drain region, and the application of an LDD (Lightly Doped Drain) structure has been considered wherein a n-type semiconductor region relatively low in impurity concentration is formed between a punch-through stopper layer and an n type semiconductor region constituting the drain region. However, the LDD structure is still accompanied by the problem in that since a region in which an electric field lying in a channel horizontal direction reaches the maximum, is placed under an insulating film provided on sidewalls of a floating gate electrode, the efficiency of injection of HE at writing is reduced.
An object of the present invention is to provide a technology capable of preventing a drain disturb phenomenon in a nonvolatile memory semiconductor device having nonvolatile memory cells for a short channel.
Another object of the present invention is to provide a technology capable of improving the efficiency of injection of HE at writing and achieve the speeding up of a write operation in a nonvolatile memory semiconductor device having nonvolatile memory cells for a short channel.
The above, other objects, and novel features of the present invention will become apparent from the following description of the present specification and the accompanying drawings.
Summaries of typical ones of the inventions disclosed in the present application will be described in brief as follows:
(1) A parallel connection-type nonvolatile memory semiconductor device of the present invention comprises a plurality of memory cells arranged on a semiconductor substrate in matrix form. Each of the plurality of memory cells includes a gate insulating film, a floating gate electrode, an interlayer film and a control gate electrode successively formed so as to cover a channel region on a main surface of the semiconductor substrate, of a first conductivity type; a second conductivity type source and drain regions formed on the semiconductor substrate on both sides opposite to each other, of the floating gate electrode so as to interpose a channel region located under the floating gate electrode therebetween; a first semiconductor region which is adjacent to the drain region and formed by introducing a second conductivity type impurity in the direction of the channel region placed under the floating gate electrode from an end on the drain side, of the floating gate electrode, and which is substantially lower than the drain region in impurity concentration; and a punch-through stopper layer which is adjacent to the first semiconductor region and formed by introducing an impurity of a first conductivity type in the direction of the channel region placed under the floating gate electrode from an end on the drain side, of the floating gate electrode, and which has an impurity concentration relatively higher than that of the channel region.
The source and drain regions of the plurality of memory cells are parallel-connected to one another in respective columns. Word lines some of which constitute the control gate electrodes of the plurality of memory cells, extend in respective rows. A voltage is applied to at least one word line, which in turn is set so as to serve as a selected word line. When carriers are stored in a floating gate electrode of a selected memory cell, a negative voltage is applied to non-selected word lines other than the selected word line.
(2) A method of manufacturing a semiconductor device, according to the present invention comprises the steps of forming a gate insulating film covering a channel region on a main surface of a semiconductor substrate of a first conductivity type, a floating gate electrode, an interlayer film and a control gate electrode; forming a second conductivity type source and drain regions on the semiconductor substrate on both sides opposite to each other, of the floating gate electrode so as to interpose a channel region located under the floating gate electrode therebetween; introducing an impurity of a first conductivity type into the semiconductor substrate from an end on the drain side, of the floating gate electrode to thereby form a punch-through stopper layer adjacent to the drain region and having an impurity concentration relatively higher than that of the channel region; and introducing an impurity of a second conductivity type into the semiconductor substrate from an end on the drain side, of the floating gate electrode to thereby form a first semiconductor region adjacent to the drain region and substantially lower than the drain region in impurity concentration.
According to the above means, a first semiconductor region substantially lower than a drain region in impurity concentration is formed between the drain region and a punch-through stopper layer, so that an electric field at a junction of the punch-through stopper layer is relaxed. Thus, even if the punch-through stopper layer having the function of preventing a short channel effect is provided and a negative voltage is applied to a control gate electrode of each non-selected memory cell to suppress a leak current developed in the non-selected memory cell upon writing, a drain disturb phenomenon can be prevented from occurring.
Further, since a punch-through stopper layer and a first semiconductor region substantially lower than a drain region in impurity concentration are provided below a floating gate electrode, a channel region to which an electric field lying in a channel horizontal direction is applied, becomes wide. Thus, the number of electrons accelerated until they have energy necessary for the injection of HE, increases and the efficiency of the injection of HE at the writing of data into each memory cell can be enhanced.
Other means of the present invention will become apparent from the description of embodiments which refer to the following drawings.